The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In today's point-to-point communication protocols, like Peripheral Component Interconnect Express (PCIe) and MIPI UniPro, multiple traffic classes or “TCs” may be supported. A traffic class enables data, such as data packets, to be streamed between a so-called “local” side and a “remote” side. PCIe, for example, is a serial expansion bus standard for connecting a computer to one or more peripheral devices. Peripheral devices can include graphics adapter cards, network interface cards (NICs), storage accelerator devices and other high-performance peripherals.
Each traffic class has its own credit flow control mechanism. The term “credit” refers to the buffer space that is available for each traffic class. To date, credit flow control mechanisms control individual traffic classes independently. This means, for example, for a system that supports two separate traffic classes TC0 and TC1, each individual traffic class is required to have its own separate receiver buffers for flow control. This results in duplicated logic which is not shareable amongst the different traffic classes. For example, some advanced systems on-chip (SOCs) support a wide range of applications that may require high throughput for high-profile scenarios, and low throughput but low power for low-profile cases. In some cases, the TC1 traffic may be higher than the TC0, which may require a larger TC1 buffer for better performance. Yet, because of the independent nature and management of the receiver buffers for each traffic class, TC1 is unable to utilize additional buffer space. This is sub-optimal and can lead to inefficiencies when, for example, all the storage space may not necessarily be needed or used.